1. Field of the Invention
The present invention relates to a method of testing a non-volatile memory called, for example, flash memory or other non-volatile memory and an apparatus for testing a non-volatile memory used in implementing such memory testing method.
2. Description of the Related Art
A flash memory is a rewritable memory that the stored contents (data) therein is replaceable on the basis of one block by one block by electrically erasing the storage data one block by one block and thereafter, rewriting data therein one block by one block. Heretofore, such non-volatile memories including flash memories have been tested and measured by a memory testing apparatus adapted for testing and measuring commonplace memories (for example, IC memories constituted by semiconductor integrated circuits). FIG. 7 shows, in block diagram, an outline of the construction of a prior typical memory testing apparatus.
The illustrated memory testing apparatus comprises a timing generator 11, a pattern generator 12, a waveform shaping device 13, a logical comparator 14, a failure analysis memory 15 and a failure history storage memory 16. Further, for clarity of explanation, other components and/or circuits of the testing apparatus will not be shown. It is needless to say that the construction of the memory testing apparatus is not limited to such construction as mentioned above.
The pattern generator 12 outputs an address ADRD, a test pattern data PTND, and a control signal CTLD, all of which are to be applied to a memory under test DUT, in accordance with a reference clock CLK supplied to the pattern generator 12 from the timing generator 11. In addition, the pattern generator 12 supplies a reference clock control signal CLKCTLD to the timing generator 11 thereby to control the reference clock generated in the timing generator 11.
The address ADRD, the test pattern data PTND, and the control signal CTLD outputted from the pattern generator 12 are shaped into an address signal ADR, a test pattern signal PTN, and a control signal CTL respectively all of which have their real waveforms in the waveform shaping device 13, and then, they are applied to the memory under test DUT.
In the memory under test DUT, writing and reading the test pattern signal PTN in and from the memory under test are carried out on the basis of the control signal CTL. A response data signal RPS read out of the memory under test DUT is given to the logical comparator 14 where it is compared with an expected value pattern data EXP supplied from the pattern generator 12, thereby to determine whether or not the memory under test DUT has outputted a proper (pass) response data signal.
The logical comparator 14 determines, when the response data signal RPS inputted thereto does not coincide with the expected value pattern data EXP, that a memory cell of the memory under test DUT at the address thereof from which that response data signal RPS has been read out is defective or failure, and generates a decision result of failure xe2x80x9cfailurexe2x80x9d and a failure data FAIL. Usually, when the failure data FAIL is generated, a logical xe2x80x9c1xe2x80x9d signal being always applied to a data input terminal of the failure analysis memory 15 is enabled to be written in the failure analysis memory 15, and the logical xe2x80x9c1xe2x80x9d data is written as the failure data FAIL in a memory cell of the failure analysis memory 15 at the address thereof specified by an address ADRD supplied from the pattern generator 12.
In general, the failure analysis memory 15 has the same address space or area as that of the memory under test DUT, and a failure data FAIL (or logical value xe2x80x9c1xe2x80x9d) is stored in the same address of the failure analysis memory 15 as that of the failure memory cell of the memory under test DUT.
On the contrary, when the response data signal RPS from the memory under test DUT coincides with the expected value pattern data EXP from the pattern generator 12, the logical comparator 14 determines that a memory cell of the memory under test DUT at the address thereof from which the response data signal RPS has been read out is a good or defectless (pass) one, and generates a decision result of pass xe2x80x9cpassxe2x80x9d.
In this manner, a determination of pass or failure of the memory under test DUT is carried out in the logical comparator 14. The result of determination of pass or failure xe2x80x9cpass/failurexe2x80x9d rendered by the logical comparator 14 is supplied to the failure history storage memory 16 and the pattern generator 12. Further, the address of the memory cell of the memory under test DUT that has been determined to be failure will be hereinafter referred to as failure cell address.
In the failure history storage memory 16 are stored an address ADRD, a test pattern data PTND and a control signal CTLD all being generated from the pattern generator 12 when a failure has been generated as well as a failure data FAIL generated from the logical comparator 14.
FIG. 8 is a block diagram showing an example of the internal construction of the pattern generator 12. The pattern generator 12 comprises an address generator 12A, a test pattern data generating part 12B, a control signal generating part 12C, and a sequence controller 12D for controlling the components 12A, 12B 12C.
The sequence, controller 12D comprises an instruction memory 12D-1 in which a series of instructions for pattern generation are previously stored, a program counter 12D-2 for specifying each of addresses of the instruction memory 12D-1, and a program counter controller 12D-3 for controlling the program counter 12D-2 on the basis of data supplied from the instruction memory 12D-1.
In each of the addresses of the instruction memory 12D-1 are previously stored a sequence control instruction, an address operation or computation instruction, a pattern data operation or computation instruction, and a control signal generation instruction. An address outputted from the program counter 12D-2 accesses the corresponding address of the instruction memory 12D-1 so that the storage data in that address is given to the program counter controller 12D-3, the address generator 12A, the pattern data generating part 12B and the control signal generating part 12C.
The program counter controller 12D-3 controls to generate the next address that is outputted from the program counter 12D-2 to the instruction memory 12D-1 in accordance with an instruction given to the controller 12D-3 from the instruction memory 12D-1. The address generator 12A, the pattern data generating part 12B, and the control signal generating part 12C generate an address ADRD, a test pattern data PTND, and a control signal CTLD all of which are to be applied to the memory under test DUT, respectively, in accordance with instructions given to them respectively from the instruction memory 12D-1. In addition, the pattern data generating part 12B also generates an expected value pattern data EXP to be applied to the logical comparator 14 in accordance with an instruction given to the generating part 12B from the instruction memory 12D-1.
FIG. 9 is a block diagram showing an example of the internal construction of the failure history storage memory 16. The failure history storage memory 16 comprises a failure address storage memory 16A for storing therein an address ADRD being outputted from the pattern generator 12 when a decision result of failure xe2x80x9cfailurexe2x80x9d has been generated from the logical comparator 14; a fail pattern data storage memory 16B for storing therein a test pattern data PTND being outputted from the pattern generator 12 when a decision result of failure xe2x80x9cfailurexe2x80x9d has been generated from the logical comparator 14; a fail control signal storage memory 16C for storing therein a control signal CTLD being outputted from the pattern generator 12 when a decision result of failure xe2x80x9cfailurexe2x80x9d has been generated from the logical comparator 14; a fail data storage memory 16D for storing therein a failure data FAIL being generated from the logical comparator 14 when a decision result of failure xe2x80x9cfailurexe2x80x9d has been generated from the logical comparator 14; and a storage address generating circuit 16E for outputting respective addresses of the memories 16A, 16B, 16C and 16D at which these data (signals) are to be stored respectively.
Accordingly, each time the logical comparator 14 renders a decision of failure xe2x80x9cfailurexe2x80x9d, an address ADRD, a test pattern data PTND, a control signal CTLD all being outputted from the pattern generator 12 at that time, and a failure data FAIL being outputted from the logical comparator 14 at that time are stored in these failure address storage memory 16A, fail pattern data storage memory 16B, fail control signal storage memory 16C, and fail data storage memory 16D, respectively.
The storage address generating circuit 16B is initialized at the starting time point of a test in the condition that it will output the first address (xe2x80x9c0xe2x80x9d in this example) of each of the respective storage memories 16A, 16B, 16C, and 16D, and each time the logical comparator 14 renders a decision of failure, the storage address generating circuit 16E increments an address generated thereby by +1, but it generates the first address xe2x80x9c0xe2x80x9d when the first time decision of failure is rendered. Accordingly, an address, a test pattern data, a control signal all of which are being generated when a decision of failure is rendered, and a failure data to be stored in each of the storage memories 16A, 16B, 16C, and 16D are stored at addresses thereof which are incremented by +1 starting at address 0 in the sequence of address 1, address 2, . . . , each time a decision of failure is rendered.
Now, a method of testing a non-volatile memory using the memory testing apparatus constructed above will be described.
A flash memory generally has its whole storage area divided into a plurality of blocks, and as described above, it is possible to erase the stored data in the storage area one block by one block en bloc. The flash memory has a function that data can be written in the storage area one block by one block and that data can be rewritten in the storage area one block by one block.
At the starting time point of a test, a block to be tested is defined, logical xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d is written in all of memory cells in the block to be tested, and thereafter, the storage data written in all of the memory cells in the block to be tested are erased en bloc. After such erase process, in order to inspect as to whether the storage data in each of the memory cells has been erased or not, the storage data in all of the memory cells in the block to be tested are read out. As a result of the reading of the storage data, a memory cell that the storage data therein has been erased is determined to be a good or defectless one (pass). The second time erase process is carried out for a memory cell or cells each having the storage data that has not been erased even after the first time erase process (such memory cell will be referred to as failure memory cell, hereinafter), and then, each failure memory cell again undergoes an inspection as to whether the storage data in each failure memory cell has been erased or not. In such manner, a series of operations for erasing the storage data written in all of memory cells in a block to be tested en bloc and inspecting as to whether the storage data in each memory cell has been erased or not, the series of operations being carried out after a logical signal has been written in all of memory cells in the block to be tested, will be referred to as erase test, hereinafter.
When the storage data in all of the memory cells have been erased within a predetermined times of erases, that block is determined to be a good or defectless one (pass). The above-mentioned erase test is repeated for all blocks in sequence, and when all blocks have been determined to be good ones (pass), that non-volatile memory under test has been determined to be a good memory (PASS).
FIG. 10 is a flow chart for explaining the above-mentioned erase test for a non-volatile memory in accordance with the sequence of process steps. First, in the first step SP1, the number of times of erases N is initialized to N=0. In the second step SP2, a block to be tested of the non-volatile memory under test is set, and in the third step SP3, an erasing pattern is applied to the set block to be tested, thereby to erase the storage data in each of all memory cells in the block to be tested. In the fourth step SP4, the number of times of erases N is incremented by +1 so that it becomes one time.
Next, in the fifth step SP5, all of the storage data in all memory cells in the block to be tested have been read out to inspect as to whether the storage data in each memory cell has been erased or not. In case even one memory cell the storage data of which has been not erased (failure memory cell) has been detected during the inspection, the process is branched to failure path xe2x80x9cFailxe2x80x9d reaching the sixth step SP6.
In the sixth step SP6, a decision as to whether the number of erase times N is smaller than a prescribed value or not is rendered. If the number of erase times N is smaller than the prescribed value, then the process is branched to YES path returning back to the third step SP3. In the third step SP3, an erasing pattern is again applied to the block to be tested, thereby to repeat the erase test described above.
In the sixth step SP6, if the number of erase times N exceeds the prescribed value, then the process is branched to NO path so that the block to be tested is determined to be failure xe2x80x9cFAILxe2x80x9d.
In the fifth step SP5, if it is confirmed that all of the storage data in all memory cells in the block to be tested have been erased, the process is branched to good path xe2x80x9cPassxe2x80x9d reaching the seventh step SP7. In the seventh step SP7, a decision is rendered as to whether the block to be tested is the last block or not. If it is determined that the block to be tested is the last block, the process is branched to YES path so that it is determined that the non-volatile memory under test is a good memory xe2x80x9cPASSxe2x80x9d. On the other hand, in the seventh step SP7, if it is determined that the block to be tested is not the last block, the process is branched to NO path reaching the eighth step SP8. In the eighth step SP8, a process for proceeding to the next block to be tested (incrementing the block address by +1) is applied to the memory under test, and then the process returns back to the first step SP1.
The details of the decision operations in the erase test performed in the fifth step SP5 will be described with reference to a flow chart shown in FIG. 11.
First, in a step SP5-1, the first address of the block to be tested is loaded. In a step SP5-2, a decision is rendered as to whether the storage data in the memory cell at the address to be tested (the first address) has been erased or not. If not erased (Fail), the process is branched to a step SP5-3 in which one (1) is set in a failure flag. Thereafter, in a step SP5-4, a failure data xe2x80x9cFAILxe2x80x9d is stored in the failure analysis memory 15 and the failure history storage memory 16, and then the process proceeds to a step SP5-5. In the step SP5-5, a decision is rendered as to whether the address to be tested is the last address or not. If the address to be tested is not the last address (NO), the process is branched to a step SP5-6 in which the address to be tested is incremented by +1. Thereafter, the process returns back to the step SP5-2.
In the step SP5-5, if it is determined that the address to be tested is the last address (YES), the process is branched to a step SP5-7. In the step SP5-7, a decision is rendered as to whether the failure flag has been 1 or not. If the failure flag has not been 1, the process is branched to NO path so that the block to be tested is determined to be a good block (pass), and then, the process proceeds to the seventh step SP7 in FIG. 10. If it is determined that the failure flag has been 1, the process is branched to YES path so that the block to be tested is determined to be a failure block (Fail), and then, the process proceeds to the sixth step SP6 in FIG. 10.
FIG. 12 shows a case of the prior art in which each of the blocks in the non-volatile memory under test has eight column addresses CA of 0 to 7 and eight row addresses RA of 0 to 7, and address signals are sequentially generated as shown by arrows, that is, the address signals are generated starting at the first column address CA (0) and the first row address RA (0) through CA and RA addresses (1, 0), (2, 0), (3, 0), . . . , to (7, 0) in the column address direction, proceeding to the second RA address (1), starting at the first CA (0) and the second RA (1) through CA and RA addresses (1, 1), (2, 1), (3, 1), . . . , to (7, 1) in the column address direction, proceeding to the third RA address (2), . . . , until the last CA and RA address (7, 7) in the same sequence, and when the address signal of the last CA and RA address (7, 7) is generated, generation of the address signals is ended so that all addresses in the block to be tested are accessed.
In the erase test of the prior art described above, each time the erase test is carried out for a block to be tested, all of the memory cells in that block to be tested are always accessed irrespective of the number of times of the erase tests, that is, even though the number of the erase test times for the block is two or more, all of the memory cells in that block to be tested are always accessed. By way of example, in the block 2 shown in FIG. 12, even if a decision is rendered in the first time erase test that the storage data in the memory cells at CA and RA addresses (2, 2), (6, 3) and (5, 7) shown by oblique lines are not erased (namely, these memory cells are failure cells), all of the addresses including the addresses that have been determined to be good cells (pass) in the first time erase test are sequentially generated in the second time erase test, and the storage data in all of the memory cells in the block 2 to be tested are read out, thereby to check as to whether each of the read-out memory cells is a good one (pass) or not. In addition, in this second time erase test, if the memory cells at CA and RA addresses (2, 2), (6, 3) and (5, 7) or any one of them is determined to be failure, the third time erase test is carried out, and all of the addresses are sequentially generated again in the third time erase test, and the storage data in all of the memory cells in the block 2 to be tested are read out, thereby to check as to whether each of the read-out memory cells is pass or failure. Thereafter, as far as any failure memory cell is detected, the prescribed number of times of the erase tests will be carried out in the same manner.
For this reason, notwithstanding a small failure memory cells, a lot of time is spent in determining as to whether each of the memory cells is pass or failure, and hence there is a disadvantage that a time duration required to carry out the erase test for each block becomes long. In case of the non-volatile memory shown in FIG. 12, for clarity of explanation, it is assumed that each of the blocks is constituted by 8 bitsxc3x978 bits. However, in practical, there are cases that the memory cells in one block are constituted by several kilobits. Accordingly, a time duration required to carry out the erase test for such block becomes long more and more.
Moreover, in case a plurality of non-volatile memories are simultaneously tested, even if there exists only one non-volatile memory having its block containing one or more failure addresses, the erase test for this non-volatile memory is repeated by a prescribed number of times as far as one or more failure memory cells are detected. As a result, the remaining non-volatile memories must await until the erase test for the non-volatile memory having its block containing one or more failure addresses has been completed, notwithstanding that the erase test for each of the remaining non-volatile memories has been completed only once. Consequently, there occurs a serious drawback that the remaining non-volatile memories spend a waste of time, which results in longer test time.
In recent years, in order to reduce a testing cost, many semiconductor memory testing apparatus each being able to test and measure a multiplicity of (for example, 64) semiconductor memories at the same time have appeared, and when many non-volatile memories are simultaneously tested by such a semiconductor memory testing apparatus, there is a strong possibility that at least one non-volatile memory among them has its block including one or more failure addresses. Accordingly, the aforesaid drawback resulting in longer test time eventually brings about an increase of the testing cost.
It is an object of the present invention to provide a memory testing method and a memory testing apparatus each being capable of carry out the erase test for a non-volatile memory at high speed.
It is another object of the present invention to provide a memory testing method and a memory testing apparatus each being capable of reading out only a failure memory cell or cells in the second time and the succeeding erase tests, and inspecting as to whether the storage data in the read-out memory cell or each of the read-out memory cells has been erased.
In order to accomplish the above objects, in a first aspect of the present invention, there is provided a memory testing method wherein after data has been written in all of the memory cells in one block to be tested of a memory having its storage area divided into a plurality of blocks, an erase test has been carried out which comprises the steps of: erasing en bloc the storage data written in all of the memory cells in the block to be tested; and inspecting as to whether the storage data in each of the memory cells has been erased or not, the method comprising the steps of: in the first time erase test, sequentially reading out all of the memory cells in the block to be tested that have been erased en bloc, inspecting as to whether the storage data in each of the memory cells has been erased or not, and storing, when a failure memory cell the storage data of which has not been erased has been detected, the address of the failure memory cell; and in the second time and the succeeding erase tests in case a failure memory cell or cells have been detected, reading out only the failure memory cell or cells in the block to be tested, the address or addresses of the failure memory cell or cells having been stored, and inspecting as to whether the storage data in the failure memory cell or each of the failure memory cells has been erased or not.
In a preferred embodiment, the aforesaid memory testing method further comprises the step of determining, in case no failure memory cell has detected from the block to be tested by carrying out the erase test a plurality of times smaller than or equal to a prescribed number of times, the block to be tested to be one which has no failure memory cell, and determining, in case a failure memory cell has been still detected from the block to be tested by carrying out the erase test repetitively even the prescribed number of times, the block to be tested to be failure.
In addition, the aforesaid memory testing method further comprises the step of rendering a decision as to whether the block to be tested that has been determined to have no failure memory cell is the last block or not, and when the block to be tested is not the last block, carrying out the erase test for the next block, and when the block to be tested is the last block, rendering a decision that the memory is pass.
In a second aspect of the present invention, there is provided a memory testing apparatus comprising: an address generator generating block addresses each specifying each block of a memory under test having its storage area divided into a plurality of blocks, and all addresses of the memory cells in each block; a first failure address storage memory storing, each time a failure memory cell the storage data of which has not been erased is detected, during a erase test inspecting as to whether the storage data in each of the memory cells in a block to be tested specified by a block address generated from the address generator has been erased or not, the address of the failure memory cell, the stored failure memory cell address or addresses being read out from the first failure address storage memory in case the next erase test is carried out; a second failure address storage memory storing, each time a failure memory cell the storage data of which has not been erased is detected, during the erase test is being carried out by reading out the failure memory cell or cells stored in the first failure address storage memory, the address of the failure memory cell, the stored failure memory cell address or addresses being read out from the second failure address storage memory in case the next erase test is carried out; controller alternately switching the first failure address storage memory and the second failure address storage memory to the writing mode and the reading mode; counting means counting the number of times of data erases performed for the block to be tested; and pass/failure decision means comparing the count value counted by the counting means with a predetermined set value, and rendering a decision as to whether the data in all of the memory cells in the block to be tested have been erased or not within a predetermined number of erase times.
In a preferred embodiment, the aforesaid memory testing apparatus further comprises: a first storage address generating circuit applying a storage address to the first failure address storage memory set in the writing mode, said storage address specifying an address of the first failure address storage memory at which the address of the detected failure memory cell is stored; a second storage address generating circuit applying a storage address to the second failure address storage memory set in the writing mode, said storage address specifying an address of the second failure address storage memory at which the address of the detected failure memory cell is stored; and a read counter applying a reading address to the first failure address storage memory set in the reading mode or the second failure address storage memory set in the reading mode, said reading address specifying the address of the first failure address storage memory or the second failure address storage memory, at which the address of the failure memory cell is stored.
In addition, the aforesaid memory testing apparatus further comprises: a storage means temporarily storing the address of the failure memory cell read out from the first failure address storage memory set in the reading mode or the second failure address storage memory set in the reading mode.
With the memory testing method and the memory testing apparatus according to the present invention, in the second time and the succeeding erase tests, only failure memory cells are read out, and a decision is rendered as to whether each of the storage data in the failure memory cells has been erased or not. Therefore, a time duration required to inspect the memory cells is largely reduced in case the number of the failure memory cells is small, and a time duration required to test a non-volatile memory can be greatly reduced.